Petri-net-based implementations for FIRA weightlifting and sprint games with a humanoid robot

In this paper, the Petri net-based wireless sensor node architecture (PN-WSNA) is used to control a humanoid robot to play weightlifting and sprint games in the FIRA HuroCup league. With the PN-WSNA approach, the control scenario and decision-making for playing weightlifting and sprint games can be modeled as a PN-WSNA model. The PN-WSNA inference engine is further used to interpret and execute the PN-WSNA model according to the sensor information from visual perception. Therefore, the implementation of playing weightlifting and sprint games is achieved in terms of the PN-WSNA model instead of native code. To verify the PN-WSNA-based implementation approach, an autonomous humanoid robot equipped with a camera and a single-board computer is used for experiments, where the camera is responsible for grabbing image frames; the single-board computer is responsible for visual localization; and the PN-WSNA models the execution and locomotion command generation. Finally, several PN-WSNA models for playing weightlifting and sprint games are proposed and the experimental results are demonstrated and discussed to validate the feasibility of applying the proposed PN-WSNA-based implementation approach.     

On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC

H.264/AVC also known as MPEG 4 part 10 or JVT, is a recently established video coding standard by the Joint Video Team (JVT) of the ISO/IEC MPEG and ITU-T VCEG. The main goal of the paper is to give a broader understanding of the design considerations for the transform and quantization blocks from H.264/AVC, by presenting area and speed optimized implementations of these blocks. The area optimized design can be used in low performance applications like mobile devices, while the speed optimized designs can be used in high definition encoders. Various designs with these blocks were synthesized with 0.18 μm TSCM technology and were also implemented on a Xilinx FPGA. The resulting gate counts were anywhere from 294 to 47,762 gates and the throughput was anywhere from 6 to 2,552 M pixels/s depending on block and optimization. In addition, a system on a programmable chip implementation of the DCT and quantization blocks is presented, which uses the Xilinx Virtex II-Pro’s FPGA and its Power PC. Using this system it is possible to process 0.8 M pixels/s.

Semantics in analogical reasoning

Abstract

To have broad application or approach the capacity of ordinary human thinking, analogical reasoning programs must become more complex or their semantics must become richer, or both. Little research is being done to discover what a broad collection of semantics can contribute to general-purpose analogical reasoning. From an analysis of a small collection of words, two classes containing over 300 categories are determined representing the semantics for understanding metaphors. A broad-based collection of simple target is source metaphors is sampled with each target and source represented in terms of these categories without known influence from the respective metaphor. A computational model is developed drawing on several disciplines while using rules for the recognition and elaboration phases of reasoning. Recognition primarily involves finding and reorganizing relevant schemata within the source. Elaboration involves reorganizing and possibly adding to the target. Given each metaphor, the TisS computer program creates a new representation of each target and source including several meanings for each metaphor. A test with human subjects making aptness and agreement judgements on the generated statements is discussed, suggesting a methodology for using a rich semantic base in analogical reasoning.     

A-律μ-律压扩的C54X实现方法研究

文中描述了A-律μ-律压扩的TMS320C54X实现。首先介绍了语音信号的基本特征，对压扩理论进行了分析，接着阐述了整个算法。针对TMS320C54X芯片的具体特点，提出了系统要求与编码方案，结合芯片软硬件条件，详尽讨论了A-律μ-律压扩的DSP编码实现过程。最后验证了代码的速度并给出了对存储空间的要求。通过对芯片软硬件资源的充分利用，使所需的MIPS和对内存的要求同时降至理想状态。     

Strategic alignment of ERP implementation stages: An empirical investigation

We applied the notion of strategic alignment to ERP system implementation and used a balanced scorecard approach to analyze business performance. The PLS analysis showed a positive association between realized strategic alignment, shorter and more cost efficient ERP projects, faster reaction times to business events, and the benefits of ERP systems. While each stage of ERP implementation has its inherent intricacies, we concluded that there was a substantial interdependency between the stages of ERP implementation and the success factors in one stage influencing the success of another.     

Evaluation of Well-Known Protocol Implementation Techniques for Application in Wireless Networks

Minimizing power consumption is a key requirement for mobile terminals. Here we discuss how power consumption of mobile terminals is influenced by the implementation of the protocol stack in the mobile. We compare the integrated layer processing (ILP) approach with the server model and the activity thread model. ILP is expected to lead to the fastest protocol implementation, and thus to the one with the lowest power consumption. To investigate this, we have implemented the eXample Data Transfer (XDT) Protocol using all three approaches. Our measurements show that the ILP approach can be outperformed by both of the other techniques when the packet error rate of the channel exceeds a threshold of 7%. To cope with dynamic changes we propose an adaptable implementation strategy, concluding that the question of the response to errors on a wireless channel requires careful consideration.     

Parallel evolutionary training algorithms for “hardware-friendly” neural networks

In this paper, Parallel Evolutionary Algorithms for integer weightneural network training are presented. To this end, each processoris assigned a subpopulation of potential solutions. Thesubpopulations are independently evolved in parallel andoccasional migration is employed to allow cooperation betweenthem. The proposed algorithms are applied to train neural networksusing threshold activation functions and weight values confined toa narrow band of integers. We constrain the weights and biases inthe range [–3, 3], thus they can be represented by just 3 bits.Such neural networks are better suited for hardware implementationthan the real weight ones. These algorithms have been designedkeeping in mind that the resulting integer weights require lessbits to be stored and the digital arithmetic operations betweenthem are easier to be implemented in hardware. Another advantageof the proposed evolutionary strategies is that they are capableof continuing the training process ``on-chip', if needed. Ourintention is to present results of parallel evolutionaryalgorithms on this difficult task. Based on the application of theproposed class of methods on classical neural network problems,our experience is that these methods are effective and reliable.     

Input Multiplexing in Artificial Neurons Employing Stochastic Arithmetic

Artificial neural networks employing stochastic arithmetic can under certain conditions outperform those based upon conventional radix arithmetic in reduced power dissipation, silicon area and improved fault tolerance. This paper describes limitations due to the inherent variance in the stochastic signals. We introduce and compare two stochastic multiplexing schemes, inter-count and intra-count multiplexing, for accumulating the total inputs to the artificial neurons. This revised version was published online in August 2006 with corrections to the Cover Date.     

A programmable array processor architecture for flexible approximate string matching algorithms

Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don’t care, complement and classes symbols. We also simulate and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 8–340 times faster execution than a desktop computer with a Pentium 4 3.5 GHz for all algorithms when the length of the pattern is 1024.     

On the inherent weakness of conditional primitives

Some well-known primitive operations, such as compare-and-swap, can be used, together with read and write, to implement any object in a wait-free manner. However, this paper shows that, for a large class of objects, including counters, queues, stacks, and single-writer snapshots, wait-free implementations using only these primitive operations and a large class of other primitive operations cannot be space efficient: the number of base objects required is at least linear in the number of processes that share the implemented object. The same lower bounds are obtained for implementations of starvation-free mutual exclusion using only primitive operations from this class. For wait-free implementations of a closely related class of one-time objects, lower bounds on the tradeoff between time and space are presented.